The present invention relates to a semiconductor memory device incorporating a field effect transistor, and particularly to improvements in such a semiconductor memory for shortening the test time.
The storage capacity of semiconductor memory devices is making rapid progress: the capacity is quadrupled every 3 years or so. The time required for testing the operation of the memory device is increased with the increasing storage capacity.
A dynamic RAM of a 1 M words .times.1 bit configuration in which the addresses are duplexed and which has been placed on the market is shown in 1985 IEEE ISSCC, p. 238, "An 85 ns 1 Mb in a plastic DIP", Yasukazu Inoue, et al., and 1985 IEEE ISSCC, p. 240, "A 90 ns 1 Mb DRAM with Multi-Bit Test Mode", Masaki Kumanoya, et al. If, in this dynamic RAM, "0" data is written into all the memory cells and "0" data is read out of all the memory cells, and "1" data is written into all the memory cells and "1" data is read out of all the memory cells, and if the cycle time (the maximum pulse width of the RAS (row address strobe) signal) is 10 microsec., the test time T1 is given by the following equation (1): ##EQU1## With an ordinary dynamic RAM, the above-described test must be repeated for the maximum (5.5 V) and the minimum (4.5 V) voltages of the operating power source voltage range, and for the highest (70.degree. C.) and the lowest (0.degree. C.) temperatures of the operating temperature range. The total test time T2 will therefore be as follows: EQU T2=40 sec. .times.4=160 sec. . . . (2)
The test time given by the equation (2) is relatively long as a test time of an IC, and reduces the productivity.